2017
P. Siegl,
R. Buchty, and
M. Berekovic
A Bandwidth Accurate, Flexible and Rapid Simulating Multi-HMC Modelling Tool
Proceedings of the Third International Symposium on Memory Systems, MEMSYS 2017, Washington, DC, USA, October 2-5, 2017,
ACM,
2017,
ISBN 978-1-4503-5335-9/17/10
DOI,
ISBN,
RIS,
BibTex
H. Isakovic,
R. Grosu,
D. Ratasich,
J. Kadlec,
Z. Pohl,
S. Kerrison,
K. Georgiou,
K. Eder,
et al.
A Survey of Hardware Technologies for Mixed-Critical Integration Explored in the Project EMC^2
Computer Safety, Reliability, and Security - SAFECOMP 2017 Workshops, ASSURE, DECSoS, SASSUR, TELERISE, and TIPS, Trento, Italy, September 12, 2017, Proceedings,
2017
URL,
DOI,
RIS,
BibTex
S. A. A. Shah,
S. Horsinka,
B. Farkas,
R. Meyer, and
M. Berekovic
Automatic Exploration of Hardware/Software Partitioning
Design and Verification Conference (DVCon) United States 2017, February 27 - March 2, 2017 , San Jose, CA USA,
2017
RIS,
BibTex
2016
R. Meyer,
J. Wagner,
B. Farkas,
S. Horsinka,
P. Siegl,
R. Buchty, and
M. Berekovic
A Scriptable Standard-Compliant Reporting and Logging Framework for SystemC
ACM Trans. Embed. Comput. Syst.,
16(1),
2016
URL,
DOI,
RIS,
BibTex
B. Farkas,
S. A. A. Shah,
J. Wagner,
R. Meyer,
R. Buchty, and
M. Berekovic
An Open and Flexible SystemC to VHDL Workflow for Rapid Prototyping
Design and Verification Conference (DVCon) Europe 2016, October 19 - 20, 2016 Munich, Germany,
2016
RIS,
BibTex
P. Siegl,
R. Buchty, and
M. Berekovic
Data-Centric Computing Frontiers: A Survey On Processing-In-Memory
Proceedings of the Second International Symposium on Memory Systems, MEMSYS 2016, Washington, DC, USA, October 3-6, 2016,
ACM,
2016,
ISBN 978-1-4503-4305-3
DOI,
ISBN,
RIS,
BibTex
J. Naghmouchi,
S. Michalik,
R. Scheiber,
A. Reigber,
P. Aviely,
R. Ginosar,
O. Bischoff,
H. Gellis,
et al.
MacSpace - High-performance DSP for onboard image processing
DSP Day: COTS DSP chips and boards,
2016
URL,
PDF,
RIS,
BibTex
P. Siegl,
R. Buchty, and
M. Berekovic
Towards Bridging the Gap Between Academic and Industrial Heterogeneous System Architecture Design Space Exploration
Proceedings of the 2016 Workshop on Rapid Simulation and Performance Evaluation - Methods and Tools, RAPIDO@HiPEAC 2016, Prague, Czech Republic, January 18, 2016,
ACM,
2016,
ISBN 978-1-4503-4072-4
URL,
DOI,
ISBN,
RIS,
BibTex
P. Siegl,
R. Buchty,
B. Farkas,
S. A. Horsinka,
R. Meyer,
J. Wagner, and
M. Berekovic
The Past, Present and Future of the Open-Source Virtual Platform SoCRocket
Proceedings of the 2016 Workshop on Mixed Criticality Applications and Implementation Approaches, EMC^2@HiPEAC 2016, Prague, Czech Republic, January 20, 2016,
2016
RIS,
BibTex
2015
J. Wagner,
R. Meyer,
R. Buchty, and
M. Berekovic
A scriptable, standards-compliant reporting and logging extension for SystemC
Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2015 International Conference on,
2015
URL,
DOI,
RIS,
BibTex
G. Ober,
J. Naghmouchi,
O. Bischoff,
P. Aviely,
R. Nadler,
D. Guiser,
V. Messina,
R. Freddi,
et al.
A rad-hard many-core computing platform for on-board quick hyperspectral image processing and interpretation
Geoscience and Remote Sensing Symposium (IGARSS), 2015 IEEE International,
2015
DOI,
RIS,
BibTex
J. Naghmouchi,
P. Aviely,
R. Ginosar,
G. Over,
O. Bischoff,
R. Nadler,
D. Guiser,
M. Citroen,
et al.
QI2S - Quick Image Interpretation System
Data Systems in Aerospace, Proceedings of the conference, ESA-SP Vol. 732, 2015, id.51,
2015
Code,
URL,
RIS,
BibTex
R. Nair,
S. Antao,
C. Bertolli,
P. Bose,
J. Brunheroto,
T. Chen,
C. Cher,
C. Costa,
et al.
Active Memory Cube: A processing-in-memory architecture for exascale systems
IBM Journal of Research and Development,
59(23),
2015
URL,
DOI,
RIS,
BibTex
P. Siegl,
R. Buchty, and
M. Berekovic
Revealing Potential Performance Improvements By Utilizing Hybrid Work-Sharing For Resource-Intensive Seismic Applications
Proceedings of the 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2015, Turku, Finland, March 4-6, 2015,
IEEE Computer Society,
2015,
ISBN 978-1-4799-8490-9
URL,
DOI,
ISBN,
RIS,
BibTex
2014
H. Al-Khalissi,
S. A. A. Shah, and
M. Berekovic
An Efficient Barrier Implementation for OpenMP-Like Parallelism on the Intel SCC
PDP '14: Proceedings of the 2014 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing,
IEEE Computer Society,
2014,
ISBN 978-1-4799-2729-6
DOI,
ISBN,
RIS,
BibTex
S. A. Horsinka,
R. Meyer,
J. Wagner,
R. Buchty, and
M. Berekovic
On RTL to TLM Abstraction to Benefit Simulation Performance and Modeling Productivity in NoC Design Exploration
NoCArc '14: Proceedings of the 2014 International Workshop on Network on Chip Architectures,
ACM,
2014,
ISBN 978-1-4503-3064-0
DOI,
ISBN,
RIS,
BibTex
2013
B. Motruk,
J. Diemer,
P. Axer,
R. Buchty, and
M. Berekovic
Safe Virtual Interrupts Leveraging Distributed Shared Resources and Core-to-Core Communication on Many-Core Platforms
PRDC '13: Proceedings of the 2013 IEEE 19th Pacific Rim International Symposium on Dependable Computing,
IEEE Computer Society,
2013,
ISBN 978-0-7695-5130-2
DOI,
ISBN,
RIS,
BibTex
2012
B. Motruk,
J. Diemer,
R. Buchty,
R. Ernst, and
M. Berekovic
IDAMC: A Many-Core Platform with Run-Time Monitoring for Mixed-Criticality
HASE '12: Proceedings of the 2012 IEEE 14th International Symposium on High-Assurance Systems Engineering,
IEEE Computer Society,
2012,
ISBN 978-0-7695-4912-5
DOI,
ISBN,
RIS,
BibTex
2011
G. Selimis,
L. Huang,
F. Mass'e,
I. Tsekoura,
M. Ashouei,
F. Catthoor,
J. Huisken,
J. Stuyt,
et al.
A Lightweight Security Scheme for Wireless Body Area Networks: Design, Energy Evaluation and Proposed Microprocessor Design
J. Med. Syst.,
35(5),
2011
URL,
DOI,
RIS,
BibTex
2010
2009
C. Bachmann,
A. Genser,
J. Hulzink,
M. Berekovic, and
C. Steger
A low-power ASIP for IEEE 802.15.4a ultra-wideband impulse radio baseband processing
DATE '09: Proceedings of the Conference on Design, Automation and Test in Europe,
European Design and Automation Association,
2009,
ISBN 978-3-9810801-5-5
ISBN,
RIS,
BibTex
A. Genser,
C. Bachmann,
C. Steger,
J. Hulzink, and
M. Berekovic
Low-Power ASIP Architecture Exploration and Optimization for Reed-Solomon Processing
ASAP '09: Proceedings of the 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors,
IEEE Computer Society,
2009,
ISBN 978-0-7695-3732-0
DOI,
ISBN,
RIS,
BibTex
M. Berekovic,
M. Hanke,
T. Schuster,
T. Kranich, and
R. Ernst
ESL design in the context of embedded systems education
WESE '09: Proceedings of the 2009 Workshop on Embedded Systems Education,
ACM,
2009,
ISBN 978-1-4503-0021-6
DOI,
ISBN,
RIS,
BibTex
L. Yseboodt,
M. D. Nil,
J. Huisken,
M. Berekovic,
Q. Zhao,
F. Bouwens,
J. Hulzink, and
J. V. Meerbergen
Design of 100 μW Wireless Sensor Nodes for Biomedical Monitoring
Journal of Signal Processing Systems,
57,
2009
DOI,
RIS,
BibTex
E. Ladis,
I. Papaefstathiou,
R. Marchesani,
K. Tuinenbreijer,
P. Langendorfer,
T. Zahariadis,
H. C. Leligou,
L. Redondo,
et al.
Secure, Mobile Visual Sensor Networks Architecture
SECON Workshops IEEE Annual Communications Society Conference on Sensor, Mesh and Ad Hoc Communications and Networks Workshops,
2009
DOI,
RIS,
BibTex
R. Buchty,
M. Kicherer,
D. Kramer, and
W. Karl
An Embrace-and-Extend Approach to Managing the Complexity of Future Heterogeneous Systems
SAMOS '09: Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation,
Springer-Verlag,
2009,
ISBN 978-3-642-03137-3
DOI,
ISBN,
RIS,
BibTex
2008
J. Govers,
J. Huisken,
M. Berekovic,
O. Rousseaux,
F. Bouwens,
M. de Nil, and
J. V. Meerbergen
Implementation of an UWB impulse-radio acquisition and despreading algorithm on a low power ASIP
HiPEAC'08: Proceedings of the 3rd international conference on High performance embedded architectures and compilers,
Springer-Verlag,
2008,
ISBN 3-540-77559-5, 978-3-540-77559-1
ISBN,
RIS,
BibTex
F. Pratas,
G. Gaydadjiev,
M. Berekovic,
L. Sousa, and
S. Kaxiras
Low power microarchitecture with instruction reuse
CF '08: Proceedings of the 5th conference on Computing frontiers,
ACM,
2008,
ISBN 978-1-60558-077-7
DOI,
ISBN,
RIS,
BibTex
J. Penders,
B. Gyselinckx,
R. Vullers,
O. Rousseaux,
M. Berekovic,
M. D. Nil,
C. V. Hoof,
J. Ryckaert,
et al.
Human++: Emerging Technology for Body Area Networks
2008
DOI,
RIS,
BibTex
M. Berekovic,
N. J. Dimopoulos, and
S. Wong
Embedded Computer Systems: Architectures, Modeling, and Simulation, 8th International Workshop, SAMOS 2008, Samos, Greece, July 21-24, 2008. Proceedings
Systems, Architectures, Modeling, and Simulation,
2008
RIS,
BibTex
2007
C. Arbelo,
A. Kanstein,
S. Lopez,
J. Lopez,
M. Berekovic,
R. Sarmiento, and
J.-Y. Mignolet
Mapping Control-Intensive Video Kernels onto a Coarse-Grain Reconfigurable Architecture: the H.264/AVC Deblocking Filter
Design, Automation Test in Europe Conference Exhibition, 2007. DATE '07,
2007
DOI,
RIS,
BibTex
L. Yseboodt,
M. D. Nil,
J. Huisken,
M. Berekovic,
Q. Zhao,
F. Bouwens, and
J. V. Meerbergen
Design of 100 \μ\W wireless sensor nodes on energy scavengers for biomedical monitoring
SAMOS'07: Proceedings of the 7th international conference on Embedded computer systems,
Springer-Verlag,
2007,
ISBN 3-540-73622-0, 978-3-540-73622-6
ISBN,
RIS,
BibTex
S. Vassiliadis,
M. Berekovic, and
T. D. Hämäläinen
Embedded Computer Systems: Architectures, Modeling, and Simulation, 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings
Systems, Architectures, Modeling, and Simulation,
2007
RIS,
BibTex
J. W. M. Jacobs,
L. V. Engelen,
J. Kuper,
G. J. M. Smit,
S. Vassiliadis,
M. Berekovic, and
T. D. Hamalainen
Image Quantisation on a Massively Parallel Embedded Processor
Systems, Architectures, Modeling, and Simulation,
2007
DOI,
RIS,
BibTex
L. Yseboodt,
M. D. Nil,
J. Huisken,
M. Berekovic,
Q. Zhao,
F. Bouwens, and
J. L. V. Meerbergen
Design of 100 muW Wireless Sensor Nodes on Energy Scavengers for Biomedical Monitoring
Systems, Architectures, Modeling, and Simulation,
2007
DOI,
RIS,
BibTex
2006
B. D. Sutter,
B. Mei,
A. Bartic,
T. V. Aa,
M. Berekovic,
J.-y. Mignolet,
K. Croes,
P. Coene,
et al.
Hardware and a Tool Chain for ADRES
Applied Reconfigurable Computing,
2006
DOI,
RIS,
BibTex
2005
H.-J. Stolberg,
M. Berekovic,
S. Moch,
L. Friebe,
M. B. Kulaczewski,
S. Flügel,
H. Klußmann,
A. Dehnhardt,
et al.
HiBRID-SoC: A Multi-Core SoC Architecture for Multimedia Signal Processing
Journal of Vlsi Signal Processing Systems for Signal Image and Video Technology,
41,
2005
DOI,
RIS,
BibTex
2004
S. Moch,
M. Bereković,
H.-J. Stolberg,
L. Friebe,
M. B. Kulaczewski,
A. Dehnhardt, and
P. Pirsch
HIBRID-SOC: a multi-core architecture for image and video applications
ACM Sigarch Computer Architecture News,
32,
2004
DOI,
RIS,
BibTex
2003
H.-J. Stolberg,
M. Berekovic,
L. Friebe,
S. Moch,
S. Flugel,
X. Mao,
M. B. Kulaczewski,
H. Klusmann,
et al.
HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing Applications
DATE '03: Proceedings of the conference on Design, Automation and Test in Europe,
IEEE Computer Society,
2003,
ISBN 0-7695-1870-2
ISBN,
RIS,
BibTex
S. Moch,
M. Berekovi\'c,
H. J. Stolberg,
L. Friebe,
M. B. Kulaczewski,
A. Dehnhardt, and
P. Pirsch
HIBRID-SOC: a multi-core architecture for image and video applications
MEDEA '03: Proceedings of the 2003 workshop on MEmory performance,
ACM,
2003
DOI,
RIS,
BibTex
2002
M. Berekovic,
P. Pirsch,
T. Selinger,
K.-i. Wels,
C. Miro,
A. Lafage,
C. Heer, and
G. Ghigo
Architecture of an Image Rendering CoProcessor for MPEG4 Visual Compositing
Journal of Vlsi Signal Processing Systems for Signal Image and Video Technology,
31,
2002
DOI,
RIS,
BibTex
2001
M. Berekovic,
H.-J. Stolberg,
P. Pirsch, and
H. Runge
A programmable co-porcessor for MPEG-4 video
ICASSP '01: Proceedings of the Acoustics, Speech, and Signal Processing, 200. on IEEE International Conference,
IEEE Computer Society,
2001,
ISBN 0-7803-7041-4
DOI,
ISBN,
RIS,
BibTex
2000
M. Berekovic,
P. Pirsch,
T. Selinger,
K. -.-.. Wels,
C. Miro,
A. Lafage,
C. Heer, and
G. Ghigo
Architecture of an Image Rendering Co-Processor for MPEG-4 Systems
ASAP '00: Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors,
IEEE Computer Society,
2000,
ISBN 0-7695-0716-6
ISBN,
RIS,
BibTex
M. Berekovic,
P. Pirsch,
T. Selinger,
K.-I. Wels,
C. Miro,
A. Lafage,
C. Heer, and
G. Ghigo
Coprocessor architecture for MPEG4 main profile visual compositing
IEEE International Symposium on Circuits and Systems,
2000
DOI,
RIS,
BibTex
1999
H. Kloos,
M. Berekovic, and
P. Pirsch
Hardware Realisierung einer JAVA Virtual Machine für High Performance Multimedia-Anwendungen
Architektur von Rechensystemen, Systemarchitektur auf dem Weg ins 3. Jahrtausend: Neue Strukturen, Konzepte, Verfahren und Bewertungsmethoden - Vorträge der 15. GI/ITG-Fachtagung ARCS '99 und der APS'99 (Arbeitsplatzrechensysteme),
VDE-Verlag GmbH,
1999,
ISBN 3-8007-2482-0
ISBN,
RIS,
BibTex
M. Berekovic,
T. Selinger,
C. Miro,
G. Ghigo,
C. Heer,
P. Pirsch,
K.-I. Wels, and
A. Lafage
The TANGRAM co-processor for MPEG4 visual compositing
IEEE Workshop on Signal Processing Systems,
1999
DOI,
RIS,
BibTex
S. Bauer,
J. Kneip,
T. Mlasko,
B. Schmale,
J. Vollmer,
A. Hutter, and
M. Berekovic
The MPEG4 Multimedia Coding Standard: Algorithms, Architectures and Applications
Journal of Vlsi Signal Processing Systems for Signal Image and Video Technology,
23,
1999
DOI,
RIS,
BibTex
M. Berekovic,
H.-j. Stolberg,
M. B. Kulaczewski,
P. Pirsch,
H. Möller,
H. Runge,
J. Kneip, and
B. Stabernack
Instruction Set Extensions for MPEG4 Video
Journal of Vlsi Signal Processing Systems for Signal Image and Video Technology,
23,
1999
DOI,
RIS,
BibTex
1998
J. P. Wittenburg,
W. Hinrichs,
J. Kneip,
M. Ohmacht,
M. Berekovic,
H. Lieske,
H. Kloos, and
P. Pirsch
Realization of a programmable parallel DSP for high performance image processing applications
DAC '98: Proceedings of the 35th annual Design Automation Conference,
ACM,
1998,
ISBN 0-89791-964-5
DOI,
ISBN,
RIS,
BibTex
1997
1995